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Mircea-Radu Teodorescu

  • Associate Professor, Computer Science & Engineering
  • 797 Dreese Laboratories
    2015 Neil Ave
    Columbus, OH 43210
  • 614-292-7027

Honors

  • 20130201-20180101

    Early Career Award.

  • 20160101

    IEEE MICRO Top Picks from Architecture Conferences in 2015, Honorable Mention.

  • 20151101

    Nominated for Best Paper Award at HPCA 2016..

  • 20140401

    Lumley Research Award.

  • 20100101

    One of the best papers at SBAC-PAD 2010.

  • 20070101-20080101

    Intel Foundation Ph.D. Fellowship.

  • 20080101

    W. J. Poppelbaum Award.

  • 20060101

    David J. Kuck Outstanding Master's Thesis Award.

Journal Articles

2015

  • Venmugil Elango, Naser Sedaghati, Fabrice Rastello, Louis-Noël Pouchet, J. Ramanujam, Radu Teodorescu, and P. Sadayappan, 2015, "On Using the Roofline Model with Lower Bounds on Data Movement." ACM Transactions on Architecture and Code Optimization (TACO) 11, no. 4, 23/67 - 23/67.

2013

  • Timothy Miller, Nagarjuna Surapaneni, Radu Teodorescu, 2013, "Runtime failure rate targeting for energy-efficient reliability in chip microprocessors." Concurrency and Computation: Practice and Experience Special Issue of the Best Papers of SBAC-PAD 2010 25, no. 6, 790–807 - 790–807.

2011

  • Timothy N. Miller, Renji Thomas and Radu Teodorescu, 2011, "Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units." IEEE Computer Architecture Letters (CAL) 11, no. 2, 45-48 - 45-48.
  • Timothy Miller, Renji Thomas and Radu Teodorescu, 2011, "Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units." IEEE Computer Architecture Letters (CAL) 11, 1-4 - 1-4.

2008

  • Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas, 2008, "VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects." IEEE Transactions on Semiconductor Manufacturing (TSM) 21, no. 1, 3-13 - 3-13.

Unknown

  • Timothy Miller, Nagarjuna Surapaneni and Radu Teodorescu, "Runtime Failure Rate Targeting for Energy-Efficient Reliability in Chip Multiprocessors." Concurrency and Computation: Practice and Experience - Special Issue of the Best Papers of SBAC-PAD 2010

Presentations

  • "Core Tunneling: Variation-Aware Voltage Noise Mitigation in GPUs." 2016, Presented at International Symposium on High-Performance Computer Architecture (HPCA),
  • "EmerGPU: Understanding and Mitigating Resonance-Induced Voltage Noise in GPU Architectures." 2016, Presented at International Symposium on Performance Analysis of Systems and Software (ISPASS),
  • "Mitigating Parameter Variation with Dynamic Fine-Grain Body Bias." 2007, Presented at Intel PhD Fellowship Forum,
  • "Variation Aware Application Scheduling and Power Management for Chip Multiprocessors." 2008, Presented at Focus on Faculty Seminar Series, CSE Department, The Ohio State University,
  • "Architectures for Energy Efficient Computing at Ultra-low Voltages." 2010, Presented at Computer Architecture Seminar, Department of Computer Science, University of Illinois at Urbana Champaign,
  • "Designing the Next Generation Reliable Architectures." 2009, Presented at Seminar on Research Topics in Computer Science and Engineering, CSE Department, The Ohio State University,
  • "Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors." 2013, Presented at Department of Computer Science, Princeton University,
  • "Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors." 2013, Presented at Computer Engineering Seminar, University of Wisconsin-Madison,
  • "Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors." 2013, Presented at Computer Architecture Lab Seminar, Carnegie Mellon University,
  • "Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors." 2013, Presented at Computer Architecture Seminar, Cornell University,
  • "Designing Near-Threshold Microprocessors in the Era of Unpredictable Transistors." 2013, Presented at Workshop on Energy Secure Systems Architecture (ESSA), in conjunction with the International Symposium on Computer Architecture (ISCA),
  • "The Design Complexity of Program Undo Support in a General-Purpose Processor." 2005, Presented at Workshop on Complexity-Effective Design, in conjunction with the International Symposium on Computer Architecture (ISCA),
  • "Empowering Software Debugging Through Architectural Support for Program Rollback." 2005, Presented at Workshop on the Evaluation of Software Defect Detection Tools, in conjunction with Programming Language Design and Implementation (PLDI),
  • "Prototyping Architectural Support for Program Rollback Using FPGAs." 2005, Presented at IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM),
  • "Reliable Systems from Unreliable Components." 2008, Presented at Seminar on Research Topics in Computer Science and Engineering, CSE Department, The Ohio State University,
  • "Parameter Variation at NT Voltage: The Power Efficiency vs. Resilience Tradeoff." 2013, Presented at DARPA PERFECT PI Meeting,
  • "Architectures for Energy Efficient Computing at Ultra-low Voltages." 2010, Presented at Computer Architecture Lab Seminar Series, Carnegie Mellon University,
  • "Mitigating Parameter Variation with Dynamic Fine-Grain Body Bias." 2007, Presented at International Symposium on Microarchitecture (MICRO),
  • "Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors." 2013, Presented at International Symposium on Computer Architecture (ISCA),
  • "Designing Energy-Efficient Microprocessors in the Era of Unpredictable Transistors." 2014, Presented at Technical University of Cluj-Napoca,
  • "Voltage Speculation with ECC Feedback, Mitigating Frequency Variation." 2014, Presented at DARPA PERFECT PI Meeting,
  • "Boosting the Energy Efficiency of Low-Voltage Multicores." 2014, Presented at Qualcomm,
  • "Boosting the Energy Efficiency of Low-Voltage Multicores." 2014, Presented at IBM TJ Watson,
  • "Boosting the Energy Efficiency of Low-Voltage Multicores." 2013, Presented at AMD,
  • "Boosting the Energy Efficiency of Low-Voltage Multicores." 2013, Presented at Intel Corp.,
  • "Parameter Variation at NT Voltage: The Power Efficiency vs. Resilience Tradeoff." 2015, Presented at DARPA PERFECT PI Meeting,

Papers in Proceedings

2017

  • Pan, X.; Bacha, A.; Teodorescu, R. "Respin: Rethinking Near-Threshold Multiprocessor Design with Non-volatile Memory." (6 2017).
  • Pan, X.; Bacha, A.; Teodorescu, R.; IEEE, "Respin: Rethinking Near-Threshold Multiprocessor Design with Non-Volatile Memory." (1 2017).
  • Pan, Xiang, ; Bacha, Anys, ; Teodorescu, R. "Respin: Rethinking Near-Threshold Multiprocessor Design with Non-Volatile Memory." in IEEE International Parallel and Distributed Processing Symposium. (5 2017).
  • Pan, X.; Bacha, A.; Teodorescu, R. "Respin: Rethinking Near-Threshold Multiprocessor Design with Non-Volatile Memory." in 31st IEEE International Parallel and Distributed Processing Symposium (IPDPS). (1 2017).

2016

  • Thomas, R.; Sedaghati, N.; Teodorescu, R. "EmerGPU: Understanding and Mitigating Resonance-Induced Voltage Noise in GPU Architectures." in 17th IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). (1 2016).
  • Skarlatos, D.; Thomas, R.; Agrawal, A.; Qin, S. et al. "Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks." (1 2016).
  • Thomas, R.; Barber, K.; Sedaghati, N.; Zhou, L. et al. "Core Tunneling: Variation-Aware Voltage Noise Mitigation in GPUs." in 22nd IEEE International Symposium on High-Performance Computer Architecture (HPCA). (1 2016).
  • Skarlatos, D.; Thomas, R.; Agrawal, A.; Qin, S. et al. "Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks." in 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). (1 2016).
  • Xiao, Y.; Zhang, X.; Zhang, Y.; Teodorescu, R. et al. "One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation." (1 2016).
  • Renji Thomas, Kristin Barber, Naser Sedaghati, Li Zhou, Radu Teodorescu "Core Tunneling: Variation-Aware Voltage Noise Mitigation in GPUs." in International Symposium on High-Performance Computer Architecture (HPCA). (3 2016).
  • Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert Pilawa, Ulya Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas "Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks." in International Symposium on Microarchitecture (MICRO). (10 2016).
  • Skarlatos, D.; Thomas, R.; Agrawal, A.; Qin, S. et al. "Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks." (12 2016).
  • Thomas, R.; Barber, K.; Sedaghati, N.; Zhou, L. et al. "Core tunneling: Variation-aware voltage noise mitigation in GPUs." (4 2016).
  • Xiao, Y.; Zhang, X.; Zhang, Y.; Teodorescu, R. "One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation." in USENIX Security Symposium (2016). (8 2016).
  • Thomas, R.; Sedaghati, N.; Teodorescu, R. "EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures." (5 2016).
  • Renji Thomas, Naser Sedaghati, Radu Teodorescu "EmerGPU: Understanding and Mitigating Resonance-Induced Voltage Noise in GPU Architectures." in International Symposium on Performance Analysis of Systems and Software (ISPASS). (4 2016).
  • Thomas, R.; Sedaghati, N.; Teodorescu, R.; IEEE, "EmerGPU: Understanding and Mitigating Resonance-Induced Voltage Noise in GPU Architectures." (1 2016).
  • Thomas, R.; Barber, K.; Sedaghati, N.; Zhou, L. et al. "Core Tunneling: Variation-Aware Voltage Noise Mitigation in GPUs." (1 2016).
  • Xiao, Y.; Zhang, X.; Zhang, Y.; Teodorescu, R. "One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation." in 25th USENIX Security Symposium. (1 2016).
  • Yuan Xiao, Xiaokuan Zhang, Yinqian Zhang, Radu Teodorescu "One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation." in USENIX Security Symposium. (8 2016).

2015

  • Anys Bacha and Radu Teodorescu "Authenticache: Harnessing Cache ECC for System Authentication." in International Symposium on Microarchitecture (MICRO). (11 2015).
  • Bacha, A.; Teodorescu, R. "Authenticache: Harnessing Cache ECC for System Authentication." in 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). (1 2015).
  • Bacha, A.; Teodorescu, R. "Authenticache: Harnessing cache ECC for system authentication." (12 2015).
  • Bacha, A.; Teodorescu, R. "Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors." (1 2015).
  • Bacha, A.; Teodorescu, R.; ACM, "Authenticache: Harnessing Cache ECC for System Authentication." (1 2015).

2014

  • Anys Bacha and Radu Teodorescu "Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors." in International Symposium on Microarchitecture (MICRO). (12 2014).
  • Bacha, A.; Teodorescu, R.; IEEE, "Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors." (1 2014).
  • Pan, X.; Teodorescu, R. "NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle cores." (1 2014).
  • Xiang Pan and Radu Teodorescu "NVSleep: Using Non-Volatile Memory to Enable Fast Sleep/Wakeup of Idle Cores." in IEEE International Conference on Computer Design (ICCD). (10 2014).
  • Pan, X.; Teodorescu, R. "NVSleep: Using Non-Volatile Memory to Enable Fast Sleep/Wakeup of Idle Cores." in 32nd IEEE International Conference on Computer Design (ICCD). (1 2014).
  • Bacha, A.; Teodorescu, R. "Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors." in 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). (1 2014).
  • Pan, X.; Teodorescu, R.; IEEE, "NVSleep: Using Non-Volatile Memory to Enable Fast Sleep/Wakeup of Idle Cores." (1 2014).

2013

  • Anys Bacha, Radu Teodorescu "Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors." in International Symposium on Computer Architecture (ISCA). (6 2013).
  • Bacha, A.; Teodorescu, R. "Dynamic reduction of voltage margins by leveraging on-chip ECC in itanium II processors." (8 2013).

2012

  • Miller, T.N.; Thomas, R.; Teodorescu, R. "Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units." (1 2012).
  • Miller, T.N.; Thomas, R.; Teodorescu, R. "Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units." (7 2012).
  • Miller, T.N.; Thomas, R.; Pan, X.; Teodorescu, R. et al. "VRSync: Characterizing and Eliminating Synchronization-Induced Voltage Emergencies in Many-core Processors." (1 2012).
  • Miller, T.N.; Pan, X.; Thomas, R.; Sedaghati, N. et al. "Booster: Reactive Core Acceleration for Mitigating the Effects of Process Variation and Application Imbalance in Low-Voltage Chips." in 18th IEEE International Symposium on High-Performance Computer Architecture (HPCA). (1 2012).
  • Miller, T.N.; Pan, X.; Thomas, R.; Sedaghati, N. et al. "Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips." (5 2012).
  • Miller, T.N.; Thomas, R.; Pan, X.; Teodorescu, R. "VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors." (8 2012).
  • Miller, T.N.; Thomas, R.; Pan, X.; Teodorescu, R. "VRSync: Characterizing and Eliminating Synchronization-Induced Voltage Emergencies in Many-core Processors." in 39th Annual International Symposium on Computer Architecture (ISCA). (1 2012).
  • Timothy N. Miller, Xiang Pan, Renji Thomas, Naser Sedaghati, Radu Teodorescu "Booster: Reactive Core Acceleration for Mitigating the Effects of Process Variation and Application Imbalance in Low-Voltage Chips." in International Symposium on High-Performance Computer Architecture (HPCA). (2 2012).
  • Miller, T.N.; Pan, X.; Thomas, R.; Sedaghati, N. et al. "Booster: Reactive Core Acceleration for Mitigating the Effects of Process Variation and Application Imbalance in Low-Voltage Chips." (1 2012).
  • Timothy N. Miller, Xiang Pan, Renji Thomas, Naser Sedaghati, Radu Teodorescu "Booster: Reactive Core Acceleration for Mitigating the Effects of Process Variation and Application Imbalance in Low-Voltage Chips." in International Symposium on High-Performance Computer Architecture (HPCA). (2 2012).
  • Timothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu "VRSync: Characterizing and Eliminating Synchronization-Induced Voltage Emergencies in Many-core Processors." in International Symposium on Computer Architecture (ISCA). (6 2012).
  • Timothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu "VRSync: Characterizing and Eliminating Synchronization-Induced Voltage Emergencies in Many-core Processors." in International Symposium on Computer Architecture (ISCA). (6 2012).
  • Miller, T.N.; Thomas, R.; Teodorescu, R. "Mitigating the effects of process variation in ultra-low voltage chip multiprocessors using dual supply voltages and half-speed units." (1 2012).

2011

  • Naser Sedaghati, Renji Thomas, Louis-Noel Pouchet, Radu Teodorescu, P. Sadayappan "StVEC: A Vector Instruction Extension for High Performance Stencil Computation." in International Conference on Parallel Architectures and Compilation Techniques (PACT). (10 2011).
  • Timothy N. Miller, Renji Thomas and Radu Teodorescu "Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Stages." in Workshop on Energy-Efficient Design, in conjunction with the International Symposium on Computer Architecture (ISCA). (6 2011).
  • Sedaghati, N.; Thomas, R.; Pouchet, L.N.; Teodorescu, R. et al. "StVEC: A vector instruction extension for high performance stencil computation." (12 2011).

2010

  • Miller, T.; Surapaneni, N.; Teodorescu, R. "Flexible error protection for energy efficient reliable architectures." (12 2010).
  • Timothy N. Miller, Nagarjuna Surapaneni and Radu Teodorescu "Flexible Error Protection for Energy Efficient Reliable Architectures." in International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). (10 2010).
  • Timothy N. Miller, James Dinan, Renji Thomas, Bruce Adcock and Radu Teodorescu "Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches." in International Symposium on Microarchitecture (MICRO). (12 2010).
  • Miller, T.N.; Thomas, R.; Dinan, J.; Adcock, B. et al. "Parichute: Generalized turbocode-based error correction for near-threshold caches." (12 2010).

2009

  • Timothy N. Miller, Nagarjuna Surapaneni, Radu Teodorescu and Joanne Degroat "Flexible Redundancy in Robust Processor Architecture." in Workshop on Energy-Efficient Design, in conjunction with the International Symposium on Computer Architecture (ISCA). (6 2009).

2008

  • Radu Teodorescu and Josep Torrellas "Variation-Aware Application Scheduling and Power Management for CMPs." in International Symposium on Computer Architecture (ISCA). (6 2008).

2007

  • Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas "Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing." in International Symposium on Microarchitecture (MICRO). (12 2007).
  • Zhou, P.; Teodorescu, R.; Zhou, Y. "HARD: Hardware-assisted lockset-based race detection." (8 2007).
  • Teodorescu, R.; Nakano, J.; Tiwari, A.; Torrellas, J. "Mitigating parameter variation with dynamic fine-grain body biasing?." (12 2007).
  • Pin Zhou, Radu Teodorescu and Yuanyuan Zhou "HARD: Hardware-Assisted Lockset-based Race Detection." in International Symposium on High Performance Computer Architecture (HPCA). (2 2007).
  • Radu Teodorescu, Brian Greskamp, Jun Nakano, Smruti R. Sarangi, Abhishek Tiwari and Josep Torrellas "VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects." in Workshop on Architectural Support for Gigascale Integration in conjunction with the International Symposium on Computer Architecture (ISCA). (6 2007).
  • Zhou, P.; Teodorescu, R.; Zhou, Y. "HARD: Hardware-assisted lockset-based race detection." in 13th International Symposium on High-Performance Computer Architecture. (1 2007).
  • Zhou, P.; Teodorescu, R.; Zhou, Y.; IEEE, "HARD: Hardware-assisted lockset-based race detection." (1 2007).
  • Teodorescu, R.; Nakano, J.; Tiwari, A.; Torrellas, J. "Mitigating parameter variation with dynamic fine-grain body biasing." in 40th Annual IEEE/AMC International Symposium on Microarchitecture. (1 2007).
  • Teodorescu, R.; Nakano, J.; Tiwari, A.; Torrellas, J. "Mitigating parameter variation with dynamic fine-grain body biasing." (1 2007).

2006

  • S. Chen, B. Falsafi, P. B. Gibbons, M. Kozuch, T. C. Mowry, R. Teodorescu, A. Ailamaki, L. Fix, G. R. Ganger, B. Lin, S. W. Schlosser "Log-Based Architectures for Continuous Monitoring of Deployed Code." in Workshop on Architectural and System Support for Improving Software Dependability, in conjunction with International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). (10 2006).
  • Chen, S.; Falsafi, B.; Gibbons, P.B.; Kozuch, M. et al. "Log-based architectures for general-purpose monitoring of deployed code." (12 2006).

2005

  • Teodorescu, R.; Torrellas, J. "Prototyping architectural support for program rollback using FPGAs." in 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. (1 2005).
  • Radu Teodorescu and Josep Torrellas "Empowering Software Debugging Through Architectural Support for Program Rollback." in Workshop on the Evaluation of Software DefectDetection Tools, in conjunction with the Conference on Programming Language Design and Implementation (PLDI). (6 2005).
  • Radu Teodorescu and Josep Torrellas "The Design Complexity of Program Undo Support in a General-Purpose Processor." in Workshop on Complexity-Effective Design, in conjunction with the International Symposium on Computer Architecture (ISCA). (6 2005).
  • Teodorescu, R.; Torrellas, J. "Prototyping architectural support for program rollback using FPGAs." (12 2005).
  • Radu Teodorescu and Josep Torrellas "Prototyping Architectural Support for Program Rollback: An Application to Software Debugging." in Workshop on Architecture Research Using FPGA Platforms, in conjunction with the International Symposium on High-Performance Computer Architecture (HPCA). (2 2005).
  • Teodorescu, R.; Torrellas, J.; Soc, I.E.E.E.C. "Prototyping architectural support for program rollback using FPGAs." (1 2005).
  • Radu Teodorescu and Josep Torrellas "Prototyping Architectural Support for Program Rollback Using FPGAs." in IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). (4 2005).

2001

  • Nedevschi, S.; Olinic, D.; Gyongyi, Z.; Nedevschi, S. et al. "Feature based retrieval of echocardiographic images using DICOM structured reporting." in 28th Annual Meeting on Computers in Cardiology. (1 2001).
  • Nedevschi, S.; Olinic, D.; Gyongyi, Z.; Nedevschi, S. et al. "Feature based retrieval of echocardiographic images using DICOM structured reporting." (1 2001).
  • Sergiu Nedevschi, Dan Olinic, Zoltan Gyongyi, Radu Teodorescu, Sergiu Nedevschi Jr. "Feature based retrieval of echocardiographic images using DICOM structured reporting." in IEEE Computers in Cardiology. (9 2001).
  • Nedevschi, S.; Olinic, D.; Gyöngyi, Z.; Nedevschi, S. et al. "Feature based retrieval of echocardiographic images using DICOM structured reporting." (1 2001).