Guest Speaker: Yungang Bao
April 17, 2019
480 Dreese Labs
Labeled Computer Architecture: New Interfaces of Conveying High-level Software Information to Hardware
Conventional computer architecture conveys software requirements to the hardware by instruction set architecture (ISA) and virtual memory mechanism, which fail to express emerging requirements such as quality-of-service (QoS) and security. To address this challenge, we propose a new computer architecture -- Labeled von Neumann Architecture (LvNA), which enables a new hardware/software interface by introducing a hardware labeling mechanism to convey software’s semantic information such as QoS and security to the underlying hardware.
In this talk, I will present LvNA's principles and demonstrate a RISC-V based FPGA prototype (a.k.a. Labeled RISC-V) that has been already open-sourced. I will also share our experiences in an agile approach for chip design with RISC-V and Chisel, which can dramatically improve RTL programming productivity by 10X according to our experiments.
Bio: Yungang Bao is a Professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the director of Center of Advanced Computer Systems (ACS) of ICT. His research interests include computer architecture and systems and serves on program committees of ASPLOS, ISCA, MICRO, SC, ICS, etc. His research work such as Labeled von Neumann Architecture (LvNA), Hybrid Memory Trace Tool (HMTT), Partition-Based DMA Cache (absorbed and implemented in Intel's DDIO technology) and PARSEC 3.0 has been adopted by industry including Alibaba, Huawei, Intel, and the research community. He was the youngest plenary keynote speaker at China National Computer Congress (CNCC) in 2016 and was invited to give a keynote presentation at ARM Research Summit 2018. He received B.S. degree from Nanjing University in 2003 and his Ph.D. degree from ICT in 2008 and was a post-doctoral researcher at Princeton University during 2010-2012.
Host: Feng Qin